This invention relates to mask-programmable logic devices, and more particularly to a method for programming a mask-programmable logic device that allows migration to and from a user-programmable logic device to allow easier verification and/or testing.
Programmable logic devices, sometimes known as “field-programmable gate arrays” (“FPGAs”) are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing”—i.e., opening—fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. These devices generally provided the user with the ability to configure the devices for “sum-of-products” (i.e., “product term” or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P-TERM logic). More recently, such devices have been provided with specialized functional blocks, such as multipliers and multiplier/accumulator blocks for digital signal processing.
In all of the foregoing programmable logic devices, both the logic functions of particular logic elements in the device, and the interconnect for routing of signals between the logic elements, were programmable. Such devices will be referred to hereinbelow as “conventional programmable logic devices” or “user-programmable logic devices” or “field-programmable logic devices,” with the latter not to be confused with the term “field-programmable gate array” which is considered to be a subset of the type of device described by the three foregoing terms.
More recently, mask-programmable logic devices have been provided. With mask-programmable logic devices, instead of selling all users the same device, the manufacturer manufactures a partial device with a standardized arrangement of logic elements whose functions are not programmable by the user, and which lacks any routing or interconnect resources.
To program a mask-programmable logic device, the user provides the manufacturer of the mask-programmable logic device with the specifications of a desired device, which may be the configuration file for programming a comparable conventional programmable logic device. The manufacturer uses that information to add metallization layers to the partial device described above. Those additional layers program the logic elements by making certain connections within those elements, and also add interconnect routing between the logic elements. Mask-programmable logic devices can also be provided with embedded random access memory blocks, as described above in connection with conventional programmable logic devices. In such mask-programmable logic devices, if the embedded memory is configured as read-only memory or P-TERM logic, that configuration also is accomplished using the additional metallization layers.
While conventional programmable logic devices allow a user to easily design a device to perform a desired function, a conventional programmable logic device invariably includes resources that may not be used for a particular design. Moreover, in order to accommodate general purpose routing and interconnect resources, and the switching resources that allow signals from any logic element to reach any desired routing and interconnect resource, conventional programmable logic devices grow ever larger as more functionality is built into them, increasing the size and power consumption of such devices. The routing of signals through the various switching elements as they travel from one routing and interconnect resource to another also slows down signals.
The advent of mask-programmable logic devices has allowed users to prove a design in a conventional programmable logic device, but to commit the production version to a mask-programmable logic device which, for the same functionality, can be significantly smaller and use significantly less power, because the only interconnect and routing resources present on the device are those actually needed for the particular design. In addition, those resources are simple metallizations, so there are no general purpose switching elements consuming space or power, or slowing down signals.
Nevertheless, heretofore the programming of mask-programmable logic devices has been accomplished by the provision to the manufacturer of the user's programming file for the user's logic design as implemented a comparable conventional programmable logic device. The manufacturer would then make its best effort to translate that design into the most efficient possible mask-programmed logic device. However, the manufacturer could not in all cases implement the design as the user would have done.
For example, a user may have wanted the device to operate at a certain frequency of operation. Or the user design may include certain numbers of certain types of components which are available in different numbers in the different devices, so that the user would design the programming differently to account for such differences. The manufacturer could not necessarily deduce such desires from the configuration file.
Moreover, a sufficiently sophisticated user might want to create a design specifically for a mask-programmable logic device. Heretofore the necessary tools have not been available to allow a user to do that.